Circuit design involves the design and placement of many different types of components that comprise a complete circuit. Such components range from simple metal shapes, to transistors to full logic gates. A circuit may be comprised of hundreds to hundreds of thousands or millions of such components. Many of these components may have variabilities in size, structure or characteristics. Creating parameterized cell libraries is one way to automate the circuit design process. For example, if a circuit requires N different varieties of a specific gate (e.g., many inverters of different signal driving strength), the similarities that all the different inverters share may be exploited (e.g., they are all inverters, just with different sizes) to describe just one inverter which contains all of those similarities. Then the differences may be defined in a parameterized way (e.g., assign a variable to describe them with its value).
However, the construction of such a parameterized cell library, or the tailoring of such a library to a new project or technology (e.g., 45 nm Bulk CMOS, 45 nm SOI CMOS, etc.) presents a problem that the code used to describe the parameterized components has to take into account many physical variables that assume different values per project or technology. Thus, moving from one technology (e.g., 45 nm Bulk CMOS) to another (e.g., 45 nm SOI CMOS) may require extensive changes in the code, which translate to additional development and debugging time. Furthermore, even when not migrating to a new technology, there are often, within the early stages of a technology, changes in the rules (that result from gathered experience) which also require such changes.